
REV. 0
EVAL-AD1852EB
–8–
APPENDIX B – Schematics
U
M
I
C
3
3
3
3
3
3
3
3
2
2
2
2
2
2
1
1
1
1
1
I
I
Z
L
B
S
D
Z
M
L
L
L
S
M
S
S
D
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
D
D
R
1
C
1
3
1
C
1
D
V
C
V
C
G
G
1
6
4
4
T
7
T
2
T
2
T
5
2
E
4
4
E
4
E
4
V
1
2
3
8
9
1
I
1
L
1
S
T
T
T
T
C
C
I
I
I
I
I
I
I
I
I
I
I
I
I
G
G
3
2
I
D
E
I
M
M
P
I
U
H
9
1
8
D
J
I
1
T
T
T
T
3
C
2
M
9
D
2
I
2
I
2
M
2
B
2
L
2
S
5
C
4
C
2
Z
8
Z
S
L
B
M
I
I
D
M
C
C
C
Z
Z
2
R
R
6
7
1
9
1
N
U
A
O
O
O
O
1
1
1
1
1
1
1
F
F
A
C
1
C
1
C
1
1
C
1
1
A
A
D
F
6
R
R
L
L
1
A
C
1
D
C
1
2
F
6
A
D
A
S
J
S
D
R
1
1
R
R
1
S
P
A
I
I
I
M
I
0
1
2
3
4
L
I
R
D
S
1
0
0
1
0
0
1
0
1
0
S
R
I
R
I
C
M
9
M
x
0
1
0
1
J
0
0
1
1
3
9
1
8
4
2
1
6
3
P
2
1
6
R
L
R
L
R
L
R
L
3
3
3
3
D
D
D
D
D
C
1
V
D
Z
Z
1
3
5
U
U
U
2
H
4
H
6
H
1
H
1
H
8
H
1
1
9
U
U
U
D
R
R
R
R
C
G
C
C
C
2
3
4
5
1
9
8
C
7
6
D
6
1
9
8
7
2
3
4
5
R
R
R
R
R
G
R
R
R
R
1
R
R
M
C
C
D
D
D
1
D
D
5
9
4
8
3
7
2
6
1
J
P
J
S
D
C
1
D
D
R
1
D
C
1
D
U
H
U
H
U
H
1
U
H
1
1
2
3
4
5
6
9
8
1
1
M
M
M
R
D
D
1
R
1
R
1
R
S
S
S
2
6
4
0
S
I
1
2
4
C
M
D
D
S
D
1
R
1
R
S
M
S
M
C
I
0
1
2
3
4
5
6
L
1
R
D
S
1
1
1
2
2
2
1
1
1
1
1
2
2
6
5
4
3
2
2
1
1
D
S
F
S
M
M
M
M
M
C
U
C
V
E
C
C
C
C
C
C
S
C
U
C
D
A
8
2
2
F
4
R
C
6
C
1
C
1
1
9
R
R
S
7
R
1
0
J
S
S
2
4
5
6
S
S
D
D
3
1
D
O
T
U
T
D
C
1
F
6
S
V
V
C
1
C
1
F
6
2
7
T
T
D
6
D
S
S
1
R
S
U
H
1
3
1
1
U
H
4
5
6
U
H
1
2
6
1
E
9
8
7
2
3
4
5
R
R
R
R
R
G
R
R
R
D
R
R
R
R
C
G
C
C
C
2
3
4
5
1
9
8
7
6
E
E
E
D
C
1
1
D
J
R
R
E
1
1
1
1
1
1
R
3
Figure 1. SPDIF Receiver, Interface CPLD and AD1852 DAC Circuits